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musl: Update to latest
Drop upstream'ed patch Fix libgcc build with musl Detailed ChangeLog [1] [1] https://git.musl-libc.org/cgit/musl/log/?qt=range&q=1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272..2c2477da9a553c0b9b2fa18073a5dcdbe6d395af (From OE-Core rev: 88ab64956762cd51d953128262fd9bc0338a4488) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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Khem Raj
Richard Purdie
parent
7a1d68d136
commit
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@ -1,67 +0,0 @@
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From 52a37610650e7366a398dd07393d3902d2f3faa3 Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Sat, 28 Sep 2019 12:19:57 -0700
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Subject: [PATCH] Change container for riscv floating-point state to __riscv_mc_fp_state
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Match the struct elements with glibc
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glibc also uses __riscv_mc prefix, some packages like gdb uses that
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Upstream-Status: Submitted [https://www.openwall.com/lists/musl/2019/09/28/1]
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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arch/riscv64/bits/signal.h | 18 +++++++++---------
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arch/riscv64/bits/user.h | 2 +-
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2 files changed, 10 insertions(+), 10 deletions(-)
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diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h
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index 76d7ad80..aba7ab00 100644
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--- a/arch/riscv64/bits/signal.h
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+++ b/arch/riscv64/bits/signal.h
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@@ -13,25 +13,25 @@ typedef unsigned long greg_t;
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typedef unsigned long gregset_t[32];
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struct __riscv_mc_f_ext_state {
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- unsigned int f[32];
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- unsigned int fcsr;
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+ unsigned int __f[32];
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+ unsigned int __fcsr;
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};
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struct __riscv_mc_d_ext_state {
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- unsigned long long f[32];
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- unsigned int fcsr;
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+ unsigned long long __f[32];
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+ unsigned int __fcsr;
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};
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struct __riscv_mc_q_ext_state {
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- unsigned long long f[64] __attribute__((aligned(16)));
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- unsigned int fcsr;
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+ unsigned long long __f[64] __attribute__((aligned(16)));
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+ unsigned int __fcsr;
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unsigned int reserved[3];
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};
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union __riscv_mc_fp_state {
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- struct __riscv_mc_f_ext_state f;
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- struct __riscv_mc_d_ext_state d;
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- struct __riscv_mc_q_ext_state q;
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+ struct __riscv_mc_f_ext_state __f;
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+ struct __riscv_mc_d_ext_state __d;
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+ struct __riscv_mc_q_ext_state __q;
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};
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typedef union __riscv_mc_fp_state fpregset_t;
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diff --git a/arch/riscv64/bits/user.h b/arch/riscv64/bits/user.h
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index d2e383b2..9918a2fe 100644
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--- a/arch/riscv64/bits/user.h
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+++ b/arch/riscv64/bits/user.h
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@@ -5,4 +5,4 @@ struct user_fpregs_struct {
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#define ELF_NGREG 32
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typedef unsigned long elf_greg_t, elf_gregset_t[ELF_NGREG];
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-typedef struct user_fpregs_struct elf_fpregset_t;
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+typedef union __riscv_mc_fp_state elf_fpregset_t;
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--
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2.23.0
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@ -1,55 +0,0 @@
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From 59f2954fcaacd9426827c69a729e2647cb9977e5 Mon Sep 17 00:00:00 2001
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From: Palmer Dabbelt <palmer@sifive.com>
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Date: Tue, 24 Sep 2019 20:30:15 -0700
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Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines
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The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect:
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there's a backwards branch in the routine, so despite tmp being written
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at the end of the assembly fragment it cannot be allocated in one of the
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input registers because the input values may be needed for another trip
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around the loop.
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For code that follows the guarnteed forward progress requirements, he
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backwards branch is rarely taken: SiFive's hardware only fails a store
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conditional on execptional cases (ie, instruction cache misses inside
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the loop), and until recently a bug in QEMU allowed back-to-back
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store conditionals to succeed. The bug has been fixed in the latest
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QEMU release, but it turns out that the fix caused this latent bug in
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musl to manifest.
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Full disclosure: I haven't actually even compiled musl. I just guessed
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this would fix a bug introducted by the new QEMU behavior, Alistair
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(CC'd) actually checked it fixes the problem. The rest is just
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conjecture.
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Upstream-Status: Submitted
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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arch/riscv64/atomic_arch.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
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index c9765342..41ad4d04 100644
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--- a/arch/riscv64/atomic_arch.h
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+++ b/arch/riscv64/atomic_arch.h
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@@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s)
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" sc.w.aqrl %1, %4, (%2)\n"
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" bnez %1, 1b\n"
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"1:"
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- : "=&r"(old), "=r"(tmp)
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+ : "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(t), "r"(s)
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: "memory");
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return old;
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@@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
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" sc.d.aqrl %1, %4, (%2)\n"
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" bnez %1, 1b\n"
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"1:"
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- : "=&r"(old), "=r"(tmp)
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+ : "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(t), "r"(s)
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: "memory");
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return old;
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--
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2.23.0
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@ -0,0 +1,48 @@
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commit a0993f8f0f161423ecdcb754f282ffd2fe47a7b5
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Author: Rich Felker <dalias@aerifal.cx>
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Date: Wed Oct 2 09:28:03 2019 -0400
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reintroduce riscv64 struct sigcontext
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commit ab3eb89a8b83353cdaab12ed017a67a7730f90e9 removed it as part of
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correcting the mcontext_t definition, but there is still code using
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struct sigcontext and expecting the member names present in it, most
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notably libgcc_eh. almost all such usage is incorrect, but bring back
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struct sigcontext at least for now so as not to introduce regressions.
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Upstream-Status: Pending
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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diff --git a/arch/riscv64/bits/signal.h b/arch/riscv64/bits/signal.h
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index 03fe48c1..2ff4be30 100644
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--- a/arch/riscv64/bits/signal.h
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+++ b/arch/riscv64/bits/signal.h
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@@ -6,12 +6,6 @@
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# define SIGSTKSZ 8192
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#endif
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-#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
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-typedef unsigned long greg_t;
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-typedef unsigned long gregset_t[32];
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-typedef union __riscv_mc_fp_state fpregset_t;
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-#endif
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-
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typedef unsigned long __riscv_mc_gp_state[32];
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struct __riscv_mc_f_ext_state {
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@@ -41,6 +35,16 @@ typedef struct mcontext_t {
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union __riscv_mc_fp_state __fpregs;
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} mcontext_t;
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+#if defined(_GNU_SOURCE) || defined(_BSD_SOURCE)
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+typedef unsigned long greg_t;
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+typedef unsigned long gregset_t[32];
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+typedef union __riscv_mc_fp_state fpregset_t;
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+struct sigcontext {
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+ gregset_t gregs;
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+ fpregset_t fpregs;
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+};
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+#endif
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+
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struct sigaltstack {
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void *ss_sp;
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int ss_flags;
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@ -4,7 +4,7 @@
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require musl.inc
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inherit linuxloader
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SRCREV = "1f0e9f9cc2e3fa354f94e18b3b362de5f1ec7272"
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SRCREV = "2c2477da9a553c0b9b2fa18073a5dcdbe6d395af"
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BASEVER = "1.1.23"
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@ -15,8 +15,7 @@ PV = "${BASEVER}+git${SRCPV}"
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SRC_URI = "git://git.musl-libc.org/musl \
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file://0001-Make-dynamic-linker-a-relative-symlink-to-libc.patch \
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file://0002-ldso-Use-syslibdir-and-libdir-as-default-pathes-to-l.patch \
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file://0001-correct-the-operand-specifiers-in-the-riscv64-CAS-ro.patch \
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file://0001-Change-container-for-riscv-floating-point-state-to-_.patch \
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file://0001-riscv-Define-sigcontext-again.patch \
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"
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S = "${WORKDIR}/git"
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