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12e2d10541
See the patch for more details, fixes a regression in qemu causing illegal instructions in libm on powerpc, triggered by a libinput upgrade. https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=f1c56cdff09f650ad721fae026eb6a3651631f3d was the glibc code generating the instruction and triggering the issue. (From OE-Core rev: bf0e4c8bb6ba22274d17d74c1df69a78f8aa157c) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
71 lines
2.3 KiB
Diff
71 lines
2.3 KiB
Diff
target/ppc: Fix fallback to MFSS for MFFSCRN, MFFSCRNI, MFFSCE and MFFSL
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The following commits changed the code such that these instructions became invalid
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on pre 3.0 ISAs:
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bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree
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394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree
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3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree
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The hardware will handle them as a MFFS instruction as the code did previously.
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Restore that behaviour. This means applications that were segfaulting under qemu
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when encountering these instructions now operate correctly. The instruction
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is used in glibc libm functions for example.
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Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230504110150.3044402-1-richard.purdie@linuxfoundation.org/]
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Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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Index: qemu-8.0.0/target/ppc/translate/fp-impl.c.inc
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===================================================================
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--- qemu-8.0.0.orig/target/ppc/translate/fp-impl.c.inc
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+++ qemu-8.0.0/target/ppc/translate/fp-impl.c.inc
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@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *c
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{
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TCGv_i64 fpscr;
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- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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+ return trans_MFFS(ctx, a);
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+ }
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+
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REQUIRE_FPU(ctx);
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gen_reset_fpstatus();
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@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext *
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{
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TCGv_i64 t1, fpscr;
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- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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+ return trans_MFFS(ctx, a);
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+ }
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+
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REQUIRE_FPU(ctx);
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t1 = tcg_temp_new_i64();
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@@ -631,7 +637,10 @@ static bool trans_MFFSCRNI(DisasContext
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{
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TCGv_i64 t1, fpscr;
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- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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+ return trans_MFFS(ctx, a);
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+ }
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+
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REQUIRE_FPU(ctx);
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t1 = tcg_temp_new_i64();
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@@ -661,7 +670,10 @@ static bool trans_MFFSCDRNI(DisasContext
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static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
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{
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- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
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+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
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+ return trans_MFFS(ctx, a);
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+ }
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+
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REQUIRE_FPU(ctx);
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gen_reset_fpstatus();
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