mirror of
git://git.yoctoproject.org/poky
synced 2026-10-07 13:50:55 +00:00
be1442e78e
Updating the 3.19 kernel SRCREVs to integrate the following Braswell changes: 374b5d0e09ea drm/i915: Only wait for required lanes in vlv_wait_port_ready() fca99e8ee111 Revert "drm/i915: Hack to tie both common lanes together on chv" 00682f31b612 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV 654b1a4497c5 drm/i915: Implement chv display PHY lane stagger setup (From OE-Core rev: 211b631b0d7bf4df3152f4d8d626d798d023d512) Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
23 lines
556 B
BlitzBasic
23 lines
556 B
BlitzBasic
KBRANCH ?= "standard/tiny/base"
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LINUX_KERNEL_TYPE = "tiny"
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KCONFIG_MODE = "--allnoconfig"
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require recipes-kernel/linux/linux-yocto.inc
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LINUX_VERSION ?= "3.19.5"
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KMETA = "meta"
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KCONF_BSP_AUDIT_LEVEL = "2"
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SRCREV_machine ?= "374b5d0e09ea016975f3d5ab5544968f31054f52"
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SRCREV_meta ?= "7215fe431391a322c7e39f410e7b8f2a2b507892"
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PV = "${LINUX_VERSION}+git${SRCPV}"
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SRC_URI = "git://git.yoctoproject.org/linux-yocto-3.19.git;bareclone=1;branch=${KBRANCH},meta;name=machine,meta"
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COMPATIBLE_MACHINE = "(qemux86)"
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# Functionality flags
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KERNEL_FEATURES = ""
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